Hardware Secured 65nm Encryption and RISC-V Processor Cores
By: Suraj Rathod
Department: Embedded Electrical and Computer Systems
Faculty Advisor: Dr. Hamid Mahmoodi
The test plan is to design a synthesizable test vector module on FPGA to verify the chip’s functionality by writing a standard testbench. To test the chip’s IC using Arria 10 GX FPGA we send test vector inputs and compare them with precalculated test values. Characterization of chip features in power consumption, data latency, and other overheads due to Obfuscation. The chip contains two cores obfuscated and non-obfuscated. Custom design PCB interconnects IC with Tape Out and this PCB would have connectors for FPGA, Chip socket, and ATE machines. Power consumption and functionality of the Chips are verified and solid results are generated.