Optimization of Optimal Buffer Insertion Under Electromigration Effect in Nanoscale Technologies
Moiz Ahmed Khan, Josep Alberto Munguia, Luis Orellana, Bhargav Bhagawan Pawar
School of Engineering
Faculty Supervisor: Hamid Mahmoodi
Electromigration is an emerging issue for high-current-density interconnects, such as power supply lines in nanoscale integrated circuits. It results in an increase in the resistance of these power supply interconnects, leading to an increase in IR drop noise, which reduces the local supply voltage and increases delays in logic circuits. Optimal buffer insertion has been employed as a method to minimize the delay of long and capacitive interconnects. In this research, we examine how the optimal number of buffers varies as the resistance of the power supply line increases due to electromigration. Two scenarios are analyzed: one without electromigration consideration and another that accounts for it. Initially, the configuration without electromigration consideration exhibits a lower delay of approximately 7.47 × 10⁻¹⁰ seconds. However, over time, the configuration that accounts for electromigration achieves a 12.24% better delay performance at the end of the circuit's lifespan. This study highlights the importance of incorporating electromigration effects into circuit design, demonstrating its effectiveness as a mitigation strategy to enhance long-term performance and reliability.