RISC-V CPU
Ethan Garcia, Ethan Weldon, Cannek Heredia, Ryan Kwong
School of Engineering
Faculty Supervisor: Hao Jiang
The objective of this project is to develop a 32-bit RISC-V CPU. It will have a five-stage pipeline architecture to ensure the efficient use of CPU resources. The CPU will also include a branch predictor to help with branching efficiency and hazard detection logic to mitigate code hazards. We will use a simulated memory to focus on our CPU's design, as a memory could be a whole other project. Specifications: ISA: TinyRisc-v V2 Core Design: 5-Stage Pipeline (Fetch, Decode, Execute, Memory, Write-Back) Memory: Simulated Clock: 50Mhz Static branch predictor Hazard detection logic (read after write, write after read, write after write)